One type of prior nonvolatile memory is the flash erasable and electrically programmable read-only memory ("flash EPROM"). A typical flash EPROM is organized into rows and columns. Memory cells are placed at intersections of word lines and bit lines. Each word line is connected to the gates of a plurality of memory cells in one row. Each bit line is connected to the drains of a plurality of memory cells in one column. The sources of all the memory cells are connected to a common source line. The flash EPROM can be programmed, and once programmed, the entire contents of the flash EPROM can be erased by electrical erasure. A high erasing voltage V.sub.PP is made available to the source of all the cells simultaneously. This results in a full array erasure. The flash EPROM may then be reprogrammed with new data.
One disadvantage of this prior flash EPROM structure is the characteristics of array erasure. When changes are sought to be made to a program stored in the array, the entire array must be erased and the entire program be rewritten into the array, even when the changes are minor.
One prior approach to solving this problem is to reorganize the array into blocks so that the high erasing voltage is made available only to the source of every cell within one block to be erased. In this arrangement, each block can be individually addressed for read, programming, and erasure operations. By this arrangement, only a block of memory array is erased, rather than having the entire memory array erased.
FIG. 1 illustrates such a typical prior arrangement. In FIG. 1, memory cells of prior flash EPROM 10 are organized into a plurality of bit line blocks BLOCK0 through BLOCKn. Each block can be individually addressed for read, programming, and erasure operations. Each block includes a plurality of bit lines that are connected to sense amplifiers 34 via a respective one of Y gating circuits 30a through 30n. Each of Y gating circuits 30a-30n includes a plurality of column select transistors for selectively connecting eight bit lines (i.e., one byte) at a time from the respective block to sense amplifiers 34. Therefore, each of Y gating circuits 30a-30n includes eight connection lines connected to sense amplifiers 34, respectively. The outputs of sense amplifiers 34 are coupled to data pins of the prior flash EPROM via data lines 35 and via output buffers in logic circuitry 20. Prior flash EPROM 10 also includes a plurality source switches 32a through 32n, each associated with one of blocks BLOCK0 through BLOCKn.
During the read operation, a Y and block decoder 17 selects one byte of bit lines of a selected block for any given address applied. The selected bit lines of the selected block are then connected to sense amplifiers 34 via the associative Y gating circuit. One of X decoders 13 and 14 selects a word line. Sense amplifiers 34 then sense the voltage levels on the selected bit lines to obtain data from the selected memory cells at intersections of the selected bit lines and the selected word line. Sense amplifiers 34 then apply the sensed data to the data pins of prior flash EPROM 10 via data lines 35 and logic circuitry 20.
During the programming operation, decoder 17 selects one byte of bit lines in a selected block for each address applied. One of X decoders 13-14 selects a word line. Programming potentials are applied to the selected bit lines and the selected word line. Decoder 17 selects the source switch associated with the selected block to couple a ground potential V.sub.SS to the sources of the memory cells of the selected block and to couple a disturb inhibit potential V.sub.DI to the sources of the memory cells of unselected blocks. This is done to help prevent the programming of the selected cells in the selected block from disturbing the memory cells in unselected blocks. During the erasure operation, decoder 17 selects one block by selecting its associative source switch for each address applied. The selected source switch applies the high erasure voltage V.sub.PP to the sources of the memory cells of the selected block, thus allowing block erasure of the selected block.
Disadvantages are, however, associated with this prior blocked flash EPROM structure. One disadvantage is that during erasing of a block, some of the memory cells of the block tend to absorb more erasure current than others. This is typically referred to as current "hogging". Current hogging typically arises when, during erasing, some memory cells enter the "Zener breakdown" state while others do not. When a cell is in the Zener breakdown state, a slight voltage increase on the source may lead to a significant increase in current flow through the cell, and vice versa. When the erasing voltage along the common source line of a block varies from point to point, the voltage variations may cause the cells coupled at one point of the source line that are in the Zener breakdown state to sink most of the erasure current. The voltage variations along a source line are typically relatively significant when the memory blocks are relatively large and contain a relatively large number of memory cells. This typically requires the source line of a block to be long in order to connect to the sources of all memory cells in that block. The relatively long source line typically increases the line impedance, which in turn results in voltage variations along the source line being relatively significant.
Another disadvantage of the above-described prior flash EPROM is that the number of the blocks and the size of each of the blocks are both fixed and cannot be altered. Thus, the user of that prior flash EPROM cannot later change the size and the number of the blocks.